This invention relates generally to semiconductor devices and, more specifically, to a semiconductor device with a dielectric diffusion source and CMOS integration and a method for manufacturing the same.
The demand for semiconductor devices to be made smaller is ever present because size reduction typically increases speed and performance. Moreover, reduction of the size of components of semiconductor devices can also increase packing density, allowing a manufacturer to produce wafers having more components.
Some semiconductor devices include multiple technologies, such as bipolar and complementary metal oxide semiconductor (CMOS) technologies, on the same device. In some manufacturing processes for such devices, independent steps are undertaken to manufacture the bipolar area and the CMOS area of the device. Each individual manufacturing step may be both time consuming and costly to a manufacturer.
The present invention provides a semiconductor device and method for manufacturing the same that substantially eliminates or reduces at least some of the disadvantages and problems associated with the previously developed semiconductor devices and methods for manufacturing the same.
In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a collector region of a semiconductor substrate and forming an isolation structure adjacent at least a portion of the collector region. The method also includes forming a gate stack layer adjacent at least a portion of the isolation structure and forming a base region of the semiconductor substrate adjacent at least a portion of the collector region. The base region comprises a base link up region proximate a lateral edge of the base region. A diffusion source layer is formed adjacent at least a portion of the base link up region. The method includes removing a portion of the gate stack layer to form a base electrode adjacent a portion of the base region and a gate electrode spaced apart from the base electrode. The gate electrode is located at a complementary metal oxide semiconductor (CMOS) area of the semiconductor device.
In accordance with another embodiment, a semiconductor device includes a collector region of a semiconductor substrate and an isolation structure adjacent at least a portion of the collector region. The semiconductor device includes a base region adjacent at least a portion of the collector region. The base region comprises a base link up region proximate a lateral edge of the base region. The semiconductor device also includes a diffusion source layer adjacent at least a portion of the base link up region and a base electrode adjacent a portion of the base region. The semiconductor device includes a gate electrode spaced apart from the base electrode. The gate electrode is located at a complementary metal oxide semiconductor (CMOS) area of the semiconductor device. The base electrode and the gate electrode are formed by removing a portion of a gate stack layer located adjacent at least a portion of the isolation structure.
Technical advantages of particular embodiments of the present invention include a semiconductor device having a bipolar area and a complementary metal oxide semiconductor (CMOS) area. Particular steps in the formation of the bipolar area are integrated with the formation of the CMOS area. Such integration reduces the need for independent steps to form each area. Accordingly, time and expense associated with manufacturing the semiconductor device may be reduced.
Another technical advantage of particular embodiments of the present invention includes a semiconductor device with a diffusion source layer for a base link up region of a base region. The base region is self-aligned without selective epitaxy or chemical mechanical polishing (CMP). A dedicated base implant is not needed, thus additional time and expense associated with manufacturing the semiconductor device may be reduced. The semiconductor device can also be manufactured having a reduced size while still maintaining a high performance level.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some or none of the enumerated advantages.